Memory sharing between computer and peripheral units



Aug- 1, 1967 R. o. GUNDERSON ETAL 3,334,333

MEMORY SHARING BETWEEN COMPUTER AND PERIPHERAL UNITS 16 Sheets-Sheet 1 Filed April 16, 1964 j??? 77mm.

The/'r Afforneys.

Allg- 1 1967 R. o. GUNDERSON ETAL 3,334,333

ERIFHERAL UNITS MEMORY SHARING BETWEEN COMPUTER AND P 16 Sheets-Sheet Filed April le, 1964 I l l I l I I |l lkT- T1 \r. I l l l I l i f1; /W

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MEMORY SHARING BETWEEN COMPUTER AND PERIPHERAL UNITS 1.6 Sheets-Sheet 7 Filed April 16. 1964 F/GJ Moroseconds Clock (a) Pu/ses Timing (b) Pu/ses G2 C/eor Pulse +2 (e) Clear Pulse +2 ros/ams; 4V

Decoder (f) Timing Sign Control (g) Tim/'ng Sign o/ Read (h) Tim/ng Sign Sfrobe Pulse+2V x (l) (sal-fam) 4V Strobe PulseL2V mwa/34a) 4V Allg. 1, 1967 Ro. GUNDERSON ETAL 3,334,333

MEMORY SHARlNG BETWEEN COMPUTER AND FBRPHERAL. UNITS Filed April 16, 1964 16 Sheets-Sheet 4 E n able Decoder Decoder (6') TimmS/gna/ gi Mom Memory 0V fj( Read Transfer cya/e F/F F2-2Y i /nven/ors. Robert 0, Gunderson S/dney l.` Volent/ne George L4 Foster Augl. 1967 R. o. GUNDERSON r-:TAL 3,334,333

MEMORY SHARING BETWEEN COMPUTER AND PERIPHERAL UNITS Filed April 16, 1964 16 Sheets-Sheet 5 (Rend Currenf (TH/rife u'rrenfJ 'lmigg Signal) A! A A Reg/ sfer A7 imi/gg /gnal George L. Foster MEMORY SHARING BETWEEN COMPUTER AND PERIPHERAL UNITS signal MQ (Write Correa! Timing Signal) IZB-L (Read Correnf R Timing Signo/i I Head /3 /3 /3 /3 WHY" l I Cum?" Enable E nab/e E nab/e Enable 60'79"" l Source Drivers Drivers Drivers Drivers 50W H 7 [20 & i l /25 i so 1 y 5o I Head i Wri/e I k Dr: vers Drivers 0J i E [/24 I Jr E E /2/ L, 1 r q, 5o l i 50 Q Write Read l l Drivers I i Drivers Memory l f LC* ,4 i?

R2 (Decoder Currenf q-r/eii -rmy /Decder I 1 Tmng 5970" j l Sense Amp/:Tiers 5am .fi3 ILOmiSfrobe l r f I M /ail 1/3/ \1.l C] P l raw-i3 M Re mer rvu-13 e0 se '"1-/3/ i To Enable To Processor From ffsfucfo Logic Decoder 06600@ '/56 F/G@ /67 /74 infraction Driver /73a. J [75 -$784 [/S'a, Divide Command From }Delgoader Drivers 7k/* 17m i i ill/54 To Logical Circui/s Inventors.

Rober! 04 Gunderson Sidney L l/a/enf/ne George L Fosfer Mm K/e lee` Decoder Ne/work W Their A fiarneysL Aug. l. 1967 R. o. GUNDERSON ETAL 3,334,333

MEMORY SHARING BETWEEN COMPUTER AND PERPHEHAL UNITS 16 Sheets-Sheet Filed April 1e, 1964 1-.31 To Column :IT- Drivers /77 183e.

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Inventors. Robert 0. Gunderson Sidney L4 Valen/ine George L4 Fosfer The/r Attorneys4 fx@ om v From Counfer Decoder /70 Allgl. 1967 R. oA GUNDERSON ETAI. 3,334,333

MEMORY SHARING BETWEEN COMPUTER AND PERIPHERAL UNITS 16 Sheets-Sheet Filed April 16, 1964 VEN Inventors.

Rober 0. Gunderson Sidney L Va/en/ne George L. Foster Japosag Ja/unog Q @SEG QEMCmQ ESQ The/'r Afforneys.

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Aug. 1. 1967 R. o. GuNDERsoN ETAI. 3,334,333

MEMORY SHARING BETWEEN COMPUTER AND PERIPHERAL UNITS Filed April 16, 1964 3,6l Sheets-Sheet if -r-- M/croseconds Program *25V Program Coprro/ O Con/rol Pulse S/grm! /89 X53 25v I -600ma @oc was; '"a

Log/cal Clock WM/'croseconds l/ Pulse CL o 2 3 f 4 5 6 clam +2 C :J1 C Purses -4v V l Decoder 0 I ffm/ng v m 'e .S/'gna/ 2v New 63 4 Decoder ...ik

Core ij Inventors. OUpU 0V L w' Rober! 0 Gunderson Signa/5 l Sidney LA Volent/ne l l l George L. Fosfer Read W/'ndmg "Wr/'fe WIr/ding Ouf/Ju! Outpur Jon 7o ram Counfer 16 Sheets-Sheet l O Prog gis/er MEMORY SHARING BETWEEN COMPUTER AND PERIPHERAL UNITS v M0 0 00 d f M dmw www W mwmmMMH wimm Q mw/ s wm cn m D m wmm Waag@ x C Aug. 1, 1967 Filed April 1e, 1934 FIG/0 Inventors. Robert 0 Gunderson Sidney LA Valenfme George l.4 Foster Their A forneys.

Command Level f Array [53) Individual Commands by Columns (Array /52l H* Program Counter Row 5mg/e Slage Commands Double Sfage Commands Aug. 1, 1967 R. O. GUNDERSON ETAL MEMORY SHARING BETWEEN COMPUTER AND PERIPHERAL UNITS Filed April 16. 1964 16 Sheets-Sheet l1 F l2 Ins/roc fion Register Program Couner ---W-J F/F F/F 017555Z 2'0" NN N/o N9 Na N7 N6 N5 N4 N3 N2 Nr Se! up ol/ XX-OO-O 0 0 0 0 0 0 0 0 0 0 0 COMING/lds XX- 0l -0 0 0 0 0 0 0 0 0 0 l Setup XX-Z-O 0 0 O 0 l 0 0 0 0 0 5mg/' 5mg@ XX-03 0 0 0 O 0 l 0 0 0 0 l Commands "Laad" 0/-04*0 0 0 0 0 0 0 0 0 0 XX- 00 3 0 0 0 0 0 0 0 0 0 lr 5 "Us l,wr-oo l o o 0 o o o o "Move''ommond/ 0550610 NN N/o N9 Ns N7 N6 N5 N4 N3 N2 N/ 5er up ol/ XX 00 0 0 0 0 0 l 0 0 0 0 0 0 Commands XX-O/ 0 0 0 l 0 l 0 0 0 YX-00 0 0 l 0 l 0 0 0 0 D 637 gva xx-o/ o o 0 0 0 0 f ou e ge Commands XXOZ l l 0 0 l 0 l 0 0 l 0 XX-03 0 0 0 0 0 l 23- 04- 0 l 0 0 l l 0 0 0 l 0 0 23 -05 0 0 0 l 0 0 0 0 23- 06- 0 0 0 l 0 0 0 0 23- 07- 0 l 0 0 0 0 0 l l l n 'l 23- /0 0 0 0 0 0 0 0 0 C mMvved 23-N-o o o o o o o 0 ma s 23-/2-0 o o o o o o 23-l3 0 0 O l 0 0 0 l 23- /4 0 l 0 0 0 0 l 0 0 5mg/e Sloge Command Double Sra e J b/ F76: Com-mug 5in/dure) S/rucfure 4 b/'fs 3 b/'rs -v- 4 bfs P1 I blf W d l x v w I I I v n v I or I R X 1 F C 4 bits-QTJ b/'fs -Tf 4 bits-1 f N e T* i a n r l y x i x i l l l 1 1 1 i l L Wm" LX; NF; -CH N /bffs Word Itf2 A In ven/ors.

l l y* Y f 4 i .l godberf Clfuv/-ldrson 1 1 l' ne] a en me Word 3 wkim* o E g George L. Foster ward *4 s /2 airs j| m The/'r A Horneys Aug. l, 1967 R. O. GUNDERSON ETAL MEMORY SHARING BETWEEN COMPUTER AND PERIPHERAL UNITS Filed April 16. 1964 FIG/6 Prepare ro C alcu- 16 Sheets-Sheet 12 From XX-OO-O /afe Address of l. F/rst Word o/ W7, forkgbheid 5e, U Operand rom ey aar I xxooo xx-oo/ ggICU/fe f /fRo F/F ser (KRO) Commands I ress o l ,f-F/rsr Word "Res, /-KR0 (Compute) af Opera/7d )M0/ 0| XXO/ I f) Tesf for Compute O0/f up 0U e "sr/p00 xx-oo-o Cammond ,Rf Sir/p v/"b $1909@ Words 1f Commands Sfore Address of Campufe Addresses xxae-ol EI xx-o2/ gerend wom of o, Le, SWIM, 5mg/e R5/ Ommand (A j Word of Memory Stage Head Ouf Third Word and Acfcumu/afor Commands /'Irt'jgonmagd and Fre/d om fa onfra/ /VQ o er XX-QB- )()OJ-l Double Stage C d /To Double Sloge Commands omman s To 5mg/e Transfer Dafa from Transfer Dafa Cg/cU/Uf@ Ad- Smge w 4Main Memory from Acc. mfa 4To Offler dress (J YS) of cmmmds mo Aecomo/alor Ma/'n Memory 5mg/e Stage M0, Memory DIV/de Commands Locaf/an ofDafa calca/are Command Snc/f /f 00d f 5W@ f Move Address of TIG-3 0 Comma/7d Command Command Leef f S/yfyrfcgf /3-04-0I ,-13044 om@ 02-04-0 2s-04a Opera/1a Lasz' Word of Qomnsfer Aw .Sn/'ff TK1-3 -O era/rd Sfored /n MMU/0,0, ,o 7'0 XX. 00.0 Quot/'enf AcwmU/Ufa" Mam Memory if Adaer 5er up suny fa oep/ere ra xx-oo-a UUPUI 0 Iddcess From /3-/2-l Mam Memory o plv/sof /3-05-0 //saw l lows-0R I lazos-of z3-oso aefefmme 5e, up 5MP fo I Number of Copy pep/9;@ Wards ro be oep/@re A'fffof 3 ,fs/e4 KA opggnd Rgggm Acc. Acc. Maved Words /n F\I` ,aL-g Aoff Main @wed /MMa/n geggsrrgnga 1;0

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Inventors. Rober! 0. Gunderson Femm to Sfore Negaf/ve Slgn Sidney L VU/em-ne Block XX-00-0 {ifany} in Mam Memory Their Attorneys.

Aug. l. 1967 R. o. GUNDERSON ETAL 3,334,333

MEMORY SHARING BETWEEN COMPUTER AND PFYPHRAL UNITS Filed April 16. 1964 16 Sheets-Sheet 15 Augl. 1967 Ro. GUNDERSON ETAL 3,334,333

MEMORY SHARING BETWEEN COMPUTER AND NHIPHIHXAL UNIT:

16 Sheets-Sheet l.

Filed April i6, 1964 mi mmxwm TFE..

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Emma G maren/ors.

16' Sheets-Sheet 1b R. O. GUNDERSON ETAL SHARING BETWEEN COMPUTER AND PERIPHERAL UNlTS Aug. 1, 1967 MEMORY Filed April 16, 1964 m o n y m am d M .f r. f o L. l W1 ,w H a m .Mm W m f R 5 6 Ory u n mi mi el. III-IIJ tml New m E i I Oh E stml BQ u l .mmmuokl ESQ E E E- QQ Eug E E iJalumm. n@ ilnumm. AoluLuwm. uw umm. n@ xlvlumm. n@ llvrlumm, Ao |J1lumm. im I'Klumw. @it h@ :633 8B .Bmwmun ummw mk nl mk IW u MN MN MN WN m Aug. l, 1967 R. o. GUNDERSON ETAL 3,334,333

MEMORY SHARING BETWEEN COMPUTER AND PRPHEHAL UNITS Filed April 16, 1964 16- Sheets-Sheet 1'5 l l i O Q I 4 l l /nvenfors Robe/f 0. Gunderson Sidney L Vale/fine George Lv Foster im M1 d@ J wwf. Their Afrorneys.

United States Patent O 3,334,333 MEMORY SHARING BETWEEN CMPUTER AND PERIPHERAL UNITS Robert 0. Gunderson and Sidney L. Valentine, Torrance, and George L. Foster, Hawthorne, Calif., assignors to The National Cash Register Company, Dayton, Ohio, a corporation of Maryland Filed Apr. 16, 1964, Ser. No. 360,271 11 Claims. (Cl. S40-172.5)

This invention relates generally to electronic digital computers, and more particularly to improved means and methods for controlling the operation thereof.

In recent years considerable ettort has been expended in the computer art towards improving the flexibility and speed capabilities of computers. The present invention has similar aims, and it is accordingly one object to provide improve-d means and methods in a computer system which will improve the flexibility and speed Capabilities thereof.

The present invention also has as its object the provision of improved means and methods lfor coordinating the operation of a data processor with one or more peripheral units (such as a tape handler, or a random access unit).

Another and more specific object of the invention is to provide improved means and methods whereby the utilization of a main memory of a data processor may be shared between the data processor and one or more peripheral units in a manner so as to permit the processing of data to occur at a significantly faster rate than would otherwise be possible.

A further object of the invention is to povide improved means and methods whereby a peripheral unit may cooperate directly with the memory of a data processor while the data processor is performing other data processing operations which do not require use of the memory.

Still another object of the invention is to provide means and methods in a computer system whereby a priority is set up with respect to the use of the memory of a data processor so that the data processor and one or more peripheral units may share the memory in a manner which permits the most expeditious utilization thereof.

Yet another object -of the invention is to provide improved means and methods for controlling the initiation of cycles and control signals in a data processor so as to facilitate the cooperation of the processor with one or more peripheral units.

A still further object of the invention is to provide improved means and methods for controlling the initiation of cycles in a data processor so as to facilitate the time sharing of the memory of the processor with one or more peripheral units.

An additional object of the invention is to provide means and methods for accomplishing the foregoing operations with a minimum of required circuitry and cost.

Yet a further object of the present invention is to provide improvements in the computer system disclosed in the commonly assigned copending patent application Ser. No. 107,109, tiled May 2, 1961, now United States Patent No. 3,223,980, in accordance with any or all ofthe foregoing objects.

The specific nature of the invention as well as other features, advantages, uses and objects thereof will become apparent from the `following detailed description of an exemplary embodiment in accordance with the invention and from the accompanying drawings in which:

FIG. 1 is a schematic block diagram showing diagrammatically the general arrangement of the computer system disclosed in the aforementioned copending patent application Ser. No. 107,109, tiled May 2, 1961, now United States Patent No. 3,223,980;

Patented Aug. l, 1967 ICC FIG. 2 is a schematic diagram illustrating the preferred timing control system providing a basic computer operating cycle for the computer system shown in FIG.

FIGS. 3 and 4 are timing diagrams for illustrating waveforms of the timing signals and other waveforms produced by or for the timing control system shown in FIG. 2 for controlling the timing of the basic operating cycle, wherein in FIG. 3, the waveforms are of timing signals for the processor, and in FIG. 4, the waveforms are of timing signals for the main memory;

FIG. 5 is a schematic block diagram of the auxiliary memory illustrated more generally in FIG. l;

FIG. 5a is a detailed diagram of a portion of the auxiliary memory shown in FIG. 5;

FIG. 5b is a timing diagram for the auxiliary memory shown in FIG. 5;

FIG. 6 is a schematic block diagram of a typical main memory unit which is illustrated in FIG. 1;

FIG. 6a is a detailed diagram of a portion of the main memory unit shown in FIG. 6;

FIGS. 7a and 7b taken together, are a schematic diagram, partially in block form and broken away in parts, showing the program control system which is illustrated more generally in the block diagram in FIG. 1;

FIG. 8 is a detailed wiring diagram of a selected portion of the program control system shown in FIG. 7b for illustrating the operation of the program control system;

FIG. 9 is a timing diagram of selected signals which are produced in the operation of the program control system shown in FIGS. 7b and 8;

FIG. 10 is a diagram showing portions -of a table of the binary states of the tlip-ops of the instruction register for the various processor commands;

FIG. 11 is a table showing the binary states of the flip-flops of the program counter;

FIG. 12 is a table showing the binary states of ilipops of the instruction register and the program counter for a typical command, for illustrating typical operations of the processor;

FIG. 13 is a table showing the binary states of the Hip-flops of the instruction register and the program counter for another typical command, for illustrating the operation of the processor;

FIG. 14 is a diagram illustrating the arrangement of data for a single stage command;

FIG. 15 is a diagram illustrating the arrangement of data for a double stage command;

FIG. 16 is a command How diagram indicating exemplary commands controlled by corresponding groups of program control transformers of the program control transformer array shown in FIGS. 7a and 7b, for illustrating operation blocks common to all processor commands, single stage commands, and operation blocks specific to typical commands;

FIG. 17 is a schematic diagram illustrating how the preferred timing control system of FIG. 2 may be modied in accordance with the present invention;

FIG. 18 is a schematic diagram illustrating how, in accordance with the present invention, one or more peripheral units may be caused to cooperate with the computer system of FIGS. 1-16 using the modified timing -control system of FIG. 17, so as to advantageously share the use of the main memory units of the computer system;and

FIGS. 19 and 20 are graphs typically illustrating how the data processor may share the main memory with two peripheral units in accordance with the invention.

Like numerals designate like elements throughout the figures ofthe drawings.

The advantages and features of the present invention will be demonstrated as applied to a computer system of the type disclosed in the aforementioned commonly assigned copending patent application Ser. No. 107,109, filed May 2, 1961, now United States Patent No. 3,223,980. However, it is to be understood that the present invention is not limited to employment with such a system, but may be applied to any computer or like system where the features thereof can be used to advantage.

In order to permit the present invention to be clearly understood, the computer system disclosed in the aforementioned copending patent application will rst be described with reference to FIGS. 1-16, and then it will be shown with reference to FIGS. 17-20 how the present invention may advantageously be applied thereto. If familiarity has already been gained with respect to this patent application, the reader may skip directly to column 36 which begins the description of the present invention with reference to FIGS. 17-20.

DESCRIPTION OF THE COMPUTER SYSTEM DIS- CLOSED IN PATENT APPLICATION SER. NO. 107,109, FILED MAY 2, 1961, NOW PATENT NO. 3,223,980

Referring now to the drawings, there is illustrated in FIG. l, a simplified schematic diagram of a preferred embodiment of the computer system disclosed in the aforementioned copending patent application. The cornputer system includes: a main memory 9 having individual memory units #0, #1, #2, and #3 for storing information including programming data, working data and intermediate results in storage cells thereof, each storage cell having a one-word capacity; an auxiliary memory 13 containing various specially designated storage cells or registers; a program control system and timing control apparatus including a clock source which feeds clock signals to processor timing control circuit 22 and timing control circuits 24, 26, 28, and 30 for the respective memory units #0, #1, #2, and #3 of the main memory. As will be discussed, infra, in connection with FIG. 2, the timing control circuits are employed to define, during each basic operating cycle of the computer: (l) the timing of the operation of reading and writing data in the main memory 9 and the auxiliary memory 13, (2) the timing of the operation of the program control 10, and (3) the timing of the application of a logic clock pulse CL to the logical flip-flops in order to advance the logical sequencing of the computer.

Typically, each of the main memory units #0, #1, #2, and #3 in FIG. 1 has a storage capacity of 10,000 words providing a total storage capacity of 40,000 words. The basic information unit in the computer system is a word which consists of 12 bits plus a parity check bit. Each memory unit of main memory 9 provides an assigned address for each storage cell or stored word and each word is individually addressable by a common address register, the L register. The main memory 9 stores the program information, i.e., the commands, as well as the working data and intermediate results, and there is no restriction on the assignment of memory cells for the program or data. Information is transferred to, from, and between the various memories in the form of parallel information bits comprising one or more words which are also in parallel, i.e., each of the twelve bits of a single word as well as the words themselvies are transferred simultaneously in parallel rather than in sequence, as in a series transfer. Arithmetic operations in the adder 11a also process both complete words and their respective bits in parallel.

The auxiliary memory 13, which is included as a part of the processor, contains various special registers, including index registers 15, jump registers 16, temporary storage register 19, and an accumulator 17. The registers in the auxiliary memory 13 are accessible via the input-output lines to the S register by means of special commands or by a keyboard (not shown). The auxiliary memory 13 comprises eighty memory cells, sixty-four of which comprise the index and jump registers 1S and 16, in which each memory cell stores eighteen bits plus a parity check bit. The accumulator 17 comprises eight memory cells for storing eight words, each word containing twelve bits plus parity. The register for temporary storage 19 consists of eight memory cells for temporary internal storage which are used by the processor during the execution of certain commands.

In order to provide access to the 40,000 words stored in the main memory 9, an eighteen bit address is required. This address consists of four decimal coded binary digits of four bits each and an additional two bits for the most significant digit for individually addressing a particular one of the memory units #0, #1, #2, and #3. The auxiliary memory 13, on the other hand, is accessed by an address consisting of seven bits.

The flip-flop registers shown in block form in FIG. 1 include not only the flip-flop circuits, but also the logical networks associated therewith. In the adder 11a, blocks for input drivers Fal-12 and Gal-l2 likewise include their respective logical input networks.

A brief discussion of each Hip-flop register shown in FIG. 1 will now be presented in order to disclose the manner in which information is transferred or distributed in the computer system. Associated with the main memory 9 are the L register and the M register. The L register includes eighteen ip-ops, L1-18, and is used as the address register for the main memory 9. Flip-flops L1-16 are capable of designating an address `ranging from 0000 to 9999 to provide access to each of 10,000 storage cells in any one of the four memory units #0l-#4, and the particular memory unit is addressed by ip-ops L17-18. The M register, which comprises thirteen flip-flops, M1-13, and their associated logical networks, is employed as the input-output register for the main `memory 9, including units #0, #1, #2, and #3, wherein flip-flops M1-12 store the word of information being transferred into or out of the particular unit of the main memory, and the ip-op M13 stores the parity check bit.

The A register and the S register are provided for the auxiliary memory 13. The A register includes seven flip-Hops A1-7 and is the address register for the auxiliary memory. The function of the A register is similar to the L register in that it determines which ymemory cell in the auxiliary memory 13 will be accessed during an auxiliary memory cycle. The S register includes nineteen flip-flops, S1-S19, and their associated logical input networks and is employed as the input-output register for the auxiliary memory. The function of the S register is similar to the M register in that any information which is read from or written into the auxiliary memory 13 passes through the S register. In addition, information transferred to and from the computer system passes through the S register, as indicated by the input and output lines to the S register in FIG. 1. Flip-Hops S1-18 are used for storing information bits while flip-flop S19 stores the parity check bit during read out of either the index or jump registers. The eighteen bit storage capacity of the auxiliary memory and S register is required in order to handle the higher order addresses of cells in the main memory. During auxiliary memory cycles in which one of the cells for the accumulator 17 is accessed, only twelve bits of information, i.e., a word, is transferred from the accumulator cell and provision is made for utilizing only flip-flops S1-12 for storage of words being transferred during the ymemory cycle so that the remaining flip-ops S13-18 can then be conveniently utilized as a shift register. The operation of the auxiliary memory and the S register, in order to provide for variable length storage, will be discussed in detail later in the detailed descriptions of the timing control apparatus shown in FIG. 2 and the auxiliary memory 13 shown in FIG. 5.

The ipdlops N1-11 are used for individual selection of transformers in the program control transformer arrays 152 and 153 for controlling the operation of the computer system. Flip-flops N7-11 comprise the instruction register and are used for storing the command code or instruction while dip-flops N1-6, designated as the program counter fiip-fiops, complete the coordinate selection for the transformers in the program control transformer array 152. The T register including flip-flops T1-12 and the fiip-fiops of the remaining registers, TM, TK, and T@ provide temporary storage of certain information required and not otherwise immediately available for making decisions in the control of the sequence of operations of the computer system.

The adder 11a, in addition to its ordinary function of adding, provides for the transfer, without addition or subtraction, of information between the S and M registers and from the S iregister to the L register. The adder thus provides a convenient link between the S, L, and M registers and avoids the necessity of a direct line between these registers.

The jump register 16 is used primarily for the storage of the starting addresses of subroutines which will automatically be entered if, during the execution of certain double stage commands, certain abnormal conditions are encountered. These conditions relate to peripheral equipment and examples of these conditions comprise sensing a single indicative of the end of the paper on a high speed printer, the end of the tape on a magnetic tape handler, read or write errors detected on the magnetic tape handler, or a parity error detected while reading a punched paper tape. Any one of these conditions may occur during access to peripheral equipment and will cause predetermined subroutines while the starting addresses are stored in the jump register to take approximate action. The accumulator 17 is a register having a storage capacity of eight words of twelve `bits each. Its primary function is to store intermediate and final results of arithmetic operations. The sign of a number is not stored in the accumulator itself, but is stored by the ip-iiop K@ in the group of special flip-fiops 11a. The effective length of the accumulator may vary from one to eighth words, depending upon the length of the information, e.g., nurnber, it contains. The T@ register stores the effective length of the accumulator. If, for example, a four, live, or six digit number is in a memory field having a length of eight words, and the field is transferred from the main memory to the accumulator, the effective length of the accumulator will be two words corresponding to the number and the remaining words of the memory field which are zeroes will be ignored. Only information contained in the effective portion of the accumulator will be considered by the processor. In the above example, the six remaining words, eg., the total length of eight words less the effective length of two words, are automatically ignored when the new sum in the accumulator is used for addition arithmetic operations, if the sum is to be stored in the main memory, or if it is to be used by a command to indicate quantity.

In transferring the number from the main memory 9 to the accumulator 17, the flip-flops A1-3 in the A register and the flip-flops T1-4 in the T register are set to 7. The words in the main memory 9 are transferred to the accumulator 17 through the adder 11a. As each word is transferred to the accumulator through the adder 11a, iiip-liops A1-3 are decremented by one. If the Word being transferred contains a significant digit, the fiip-fiops T1-4 are set by tiip-fiops A1-3. After the last word is transferred from the main memory to the accumulator and in the following operating cycle, the fiip-ops T@1-3 of the T@ are set by the fiip-liops T1-4.

Any memory cell in the index registers 15, jump registers 16, or the accumulator 17 may be accessed by certain commands or manually from the input keyboard (not shown) in order to store or change the number in the addressed register. Access to the registers in the auxiliary memory 13 is provided through the S register at the address placed in the A register. The foregoing is provided by lines connected directly from the input keyboard to logical networks in the respective A and S registers.

The details of the basic data structure employed in the computer system disclosed in the aforementioned copending patent application will next be considered. Hexadecimal and decimal digits and alpha-numeric characters are employed throughout the system and are represented by four bit and six bit configurations, respectively. Sixtyfour alpha-numeric characters, comprising the upper case letters of the alphabet, some lower case letters of the alphabet, and certain symbols, are represented by a six bit configuration. The hexadecimal digits, or more simply, digits, lend themselves to binary configurations since four bits can be arranged in sixteen ways wherein 0, l, 2, 3, 4, 5, 6, 7, 8, 9, space, (&), and represent the sixteen different configurations Of four binary digits or bits. The term digit refers to any of the sixteen possible configurations obtainable with four bits, while the term character will refer to any six bit configuration.

The binary configuration of each word consisting of twelve bits may be considered as either representing characters or digits. The following illustrations are examples of a word of information wherein a six bit configuration is employed to represent the letters B and R.

A unit of information commonly exceeds the capacity of one word; therefore, a main memory field consisting of as many as eight adjoining words may be used for storage of a unit of information, e.g., a command or operand. The main memory field is variable in length to accommodate units of information varying in length. The variable length utilizes the memory capacity more efficiently and provides for greater speed in the execution of commands in which shorter units of information or operands are being accessed. Since the maximum field length for a unit of information is eight words, the maximum length of a positive number is twenty-four digits. If the unit of information is a name or description employing characters (each word having a capacity of two characters) the eight words provide a maximum length of sixteen characters. In the storage of digits, the sign of a negative number is stored in the most significant digit position and the maximum length of a negative number, not including the minus sign, is twenty-three digits` The following is an illustration of a positive number 2398645 which is stored in a memory field of live words starting at the memory address 100.

A negative sign would be stored in the most left digit position at the most significant end of the main memory field (eg. memory address 100 in the illustration), and the absence of a negative sign indicates a positive number. It will be noted that the least significant word is located at the highest order address of the memory field, as illustrated in memory address 104. The address of the rnost significant word depends on the length of the number wherein the most significant digit is in the highest order address of a word in the field containing a significant digit, as illustrated at address 102. The lower order addresses of words in the memory field which are not significant digits and are all zeroes are provided, for example, for the storage of a larger number resulting from addition, etc., to the number in the memory field, and is to be stored in the same memory field. In the foregoing axample, the field could be limited to three words to store the significant digits of the number 2398645 with the sign stored in the most significant digit position of the word at address 102.

T imng control system Referring now to FIG. 2 for a description of the timing of the computer system disclosed in the aforementioned copending patent application, a timing control system is shown diagrammatically which generates timing control signals for controlling the timing of the operations of the computer. The timing control system includes a clock source 20 for supplying clock pulses C to a group of timing control circuits including a timing control circuit 22 for the processor which includes the auxiliary memory; a timing control circuit 24 for the main memory unit and timing control circuits 26, 28, and 30 for the respective main memory units #1, #2, and #3. The timing control circuits 26, 28, and 30 for main memory units #1, #2, and #3 have not been shown in detail since each of the circuits 26, 28, and 30 is the same as the timing control circuit 24. Clock pulses C and timing signals for a typical operating cycle including an auxiliary memory cycle and a main memory cycle are illustrated in FIGS. 3 and 4.

Each of the timing control circuits includes an electric delay line, e.g., low impedance lumped constant or distributed capacity delay lines 40 and 42, and each electric delay line has a total delay of six microseconds. The total time period of delay corresponds to the time interval of an operating cycle in order to derive timing pulses P from the delay line as required during the operating cycle. As shown, each of the delay lines is divided into six equal one microsecond delay line sections, for example the processor delay line 40 includes individual one microsecond delay line sections 44 to 49 inclusive. The first section 44 of the delay line 40 is connected to the clock source 20 through an amplifier-Shaper circuit 41 for amplifying and shaping the clock pulses C. Adjacent sections of each delay line are also connected by respective am plifier-shaper circuits, e.g., amplifier-Shaper circuits 41, which amplify and shape the clock pulses C after passing through a previous section of the delay line 40.

In the embodiment as shown in FIG. 2, each delay line section is capable of being tapped between ten .1 microsecond subsections. The taps t0 to t8, tm0, tml, and m13 to tmS, are selected taps for the present embodiment and are utilized for coupling timing pulses, such as P0, P1, etc. (FIG. 3(b)), to gates and timing flip-flops in the respective timing control circuits. All of the taps between subsections have not been shown in detail but are indicated in the drawing as available between .1 microsecond time intervals over the time interval of delay of the respective delay line section whereby selected timing pulses, such as P0, P1, etc. can be made available for the timing of the operations in an operating cycle. The connections to the taps on the delay lines 40 and 42 to pulse and timing signal circuits, i.e., the gating circuits and timing flip-flops, are indicated diagrammatically for delay line section 44 as adjustable connections or sliders 31 for varying the position of the connection to the delay line of taps t0 to t8, m10, tml, and m13 to m18 for varying the time interval of the timing pulses derived from the delay lines 40 and 42. If desired, the connections from the pulse and timing circuits to respective taps l0 to t8, tm0, tml, and m13 to tmS may be fixed, e.g., solder connections.

The output of the clock source 20 is coupled to the timing control circuits to supply a clock pulse C to the delay line 40 and to a main memory decoder 12 including input gates 34, 36, 38, and 39.

Each of the timing control circuits 22, 24, 26, 28, and 30 includes a group of timing signal generating circuits, i.e., timing flip-flops, and each of the timing fiip-flops produces a low potential level (-2 v.) timing signal output when in the true state for controlling the time period in which circuits coupled to the respective timing flipfiops are made operative during an operating cycle of the data processor. A first timing pulse coupled to a flipflop in an operating cycle is coupled to its set input to set it into its true state while a second timing pulse coupled to the same flip-fiop is coupled to its reset input to reset the flip-flop to its false state. The true state outputs of the timing fiipfiops are referred to as timing signals rather than timing pulses, to distinguish from the latter.

In addition, each of the timing control circuits includes at least one strobe pulse forming circuit which is coupled to respective delay lines for passing a timing pulse which is amplified and shaped to produce strobe pulses, c g., Qal, Qa2, and Qm shown in FIGS. 3(1), 3U), and 4(g), for strobing or gating the output of respective groups of memory sense amplifiers during memory cycles including a read transfer memory cycle, i.e., reading out an addressed cell in the respective memory and storing the data in the respective groups of ip-ops comprising the respective memory register. Also, the processor timing control circuit 22 includes a pulse shaping circuit 69 which is coupled to tap 16 of the delay line 40 to provide a logical clock pulse CL (FIG. 3(k) In addition to the timing control circuits 22, 24, 26, 28, and 30, the timing control system includes clear pulse forming circuits 50 and 57 which provide clear pulses for the auxiliary and main memory respectively. The clear pulse circuits are coupled to the clock source 20 through an amplier-shaper circuit 43 to provide clear pulses R51 and Rs2 (FIGS. 3(d) and 3(e)) for clearing the S register (FIG. 5) prior to a read transfer memory cycle in the auxiliary memory; and clear pulse Rm (FIG. 4(c)) for clearing the M register (FIG. 6) prior to a read transfer memory cycle in the main memory unit #0.

The nomenclature used employs combinations of upper case letters and numbers for designating fiip-fiops (e.g. Sl) and combinations of upper case letters followed by lower case letters and numbers for drivers (eg. Ksl). The outputs of the Hip-flops are characterized by corresponding upper case letters with the associated numbers shown as a subscript (c g. S1) and the outputs of drivers by corresponding upper case letters and lower case letters with the associated numbers shown as subscripts (e.g. Kil). In order to characterize the true state output of a flip-iiop circuit or driver circuit from the false, the latter is distinguished from the former hy an affixed prime. A single logical input to a fiipop is designated by corresponding upper case letters and numbers preceded by the lower case letter s (e.g. sSl). The inputs for setting and resetting a flip-flop are distinguished by lower case letters corresponding to the flip-fiops and from one another by subscripts 1 and 0, respectively, prefixing the lower case letters (see FIG. 22a), for example, s1 and Isl.

In designating the timing pulses, the upper case letter P has been reserved which is followed by corresponding numbers, (e.g. P0, P1, etc.). The main memory timing pulses are distinguished from corresponding timing pulses P in the `processor by the lower case letter m which follows (e.g. P1110, Pml, etc.). The upper case letter C is 

9. IN A COMPUTER SYSTEM, A PROCESSOR CAPABLE OF PROCESSING DATA IN A PLURALITY OF SELF-SEQUENCING OPERATING CYCLES OF SUBSTANTIALLY EQUAL DURATION DURING EACH OF WHICH ANY ONE OF THE POSSIBLE FUNCTIONS PERFORMABLE BY SAID PROCESSOR DURING A SINGLE CYCLE FROM THE SIMPLEST TO THE MOST COMPLEX CAN BE PERFORMED, SAID PROCESSOR INCLUDING TIMING MEANS FOR INITIATING A PROCESSOR CYCLE AND FOR PROVIDING TIMING CONTROL SIGNALS DURING EACH INITIATED PROCESSOR CYCLE, SAID PROCESSOR ALSO INCLUDING A RANDOMLY ACCESSIBLY MEMORY CAPABLE OF BEING SELECTIVELY CHOSEN FOR ACCESS BY SAID PROCESSOR IN ANY ONE OR MORE OF SAID OPERATING CYCLES, SAID PROCESSOR INCLUDING MEANS OPERABLE IN EACH OPERATING CYCLE TO PROVIDE A PROCESSOR REQUEST SIGNAL INDICATING WHETHER OR NOT THE PROCESSOR REQUIRES ACCESS TO THE MEMORY DURING THE NEXT OPERATING CYCLE, MEANS INCLUDING PROCESSOR ADDRESS MEANS AND PROCESSOR INPUT-OUTPUT MEANS FOR COOPERATING WITH SAID MEMORY TO PERMIT PERFORMANCE OF A MEMORY CYCLE DURING WHICH A SELECTED ADDRESS IN MEMORY IS ACCESSED IN ACCORDANCE WITH SAID PROCESSOR ADDRESS MEANS, SAID PROCESSOR FURTHER INCLUDING PROCESSOR MEMORY ACCESS INDICATING MEANS FOR INDICATING WHEN THE PROCESSOR IS USING THE MEMORY AND PROCESSOR MEMORY REQUEST INDICATING MEANS FOR INDICATING WHETHER THE PROCESSOR REQUESTS ACCESS TO THE MEMORY DURING THE NEXT PROCESSOR CYCLE, AT LEAST ONE PERIPHERAL UNIT INCLUDING PERIPHERAL ADDRESS MEANS AND PERIPHERAL INPUT-OUTPUT MEANS CAPABLE OF COOPERATING WITH SAID MEMORY IN THE SAME MANNER AS SAID PROCESSOR ADDRESS MEANS AND SAID PROCESSOR INPUT-OUTPUT MEANS, THE PERIOD OF AN OPERATING CYCLE OF SAID PROCESSOR BEING RELATIVELY SMALL WITH RESPECT TO THE PERIOD BETWEEN TRANSFERS OF DATA BY SAID PERIPHERAL UNIT, GATING MEANS FOR GATING SAID ADDRESS MEANS AND SAID INPUT-OUT MEANS SO AS TO PERMIT EITHER THE PROCESSOR ADDRESS AND INPUTOUTPUT MEANS OR THE PERIPHERAL ADDRESS AND INPUT-OUTPUT MEANS TO ACCESS SAID MEMORY INDEPENDENTLY OF ONE ANOTHER, SAID PERIPHERAL UNIT ALSO INCLUDING PERIPHERAL REQUEST INDICATING MEANS FOR INDICATING WHEN SAID PERIPHERAL UNIT REQUESTS ACCESS TO SAID MEMORY, MEANS COUPLED TO SAID PERIPHERAL REQUEST INDICATING MEANS FOR INHIBITING SAID PERIPHERAL REQUEST INDICATING MEANS FOR INHIBITING GENERATION OF A NEW PROCESSOR CYCLE WHEN BOTH SAID PROESSOR AND SAID PERIPHERAL UNIT REQUEST ACCESS TO THE MEMORY FOR THE SAME PERIOD, AND MEANS COUPLED TO SAID PERIPHERAL REQUEST INDICATING MEANS AND SAID PROCCESSOR MEMORY ACCESS INDICATING MEANS FOR PERMITTING SAID PERIPHERAL UNIT TO ACCESS SAID MEMORY VIA SAID GATING MEANS WHEN SAID PROCESSOR IS NOT ACCESSING THE MEMORY.
 11. IN A COMPUTER SYSTEM, A PROCESSOR CAPABLE OF PROCESSING DATA IN A PLURALITY OF SELF-SEQUENCING OPERATING CYCLES OF SUBSTANTIALLY EQUAL DURATION DURING EACH OF WHICH ANY ONE OF THE POSSIBLE FUNCTIONS PERFORMABLE BY SAID PROCESSOR DURING A SINGLE CYCLE FROM THE SIMPLEST TO THE MOST COMPLEX CAN BE PERFORMED, PROCESSOR TIMING MEANS INCLUDING A DELAY LINE, A PLURALITY OF TAPPED POINTS ALONG SAID DELAY LINE FROM WHICH TIMING SIGNALS ARE DERIVED, PULSE GENERATOR MEANS FOR APPLYING A PULSE TO SAID DELAY LINE TO INITATE A PROCESSOR CYCLE, A PLURALITY OF SUMMING DIODES LOCATED AT SPACED POINTS ALONG SAID DELAY LINE, AMPLIFIER-SHAPER CIRCUIT MEANS COOPERATING WITH SAID DELAY LINE TO CONTROL THE AMPLITUDE AND SHAPE OF A PULSE PROPAGATED THEREALONG, MEANS SUMMING THE OUTPUTS OF SAID SUMMING DIODES AND APPLYING THE SUMMED OUTPUT THEREOF OF SAID PULSE GENERATOR MEANS TO INHIBIT THE GENERATION OF THE NEXT PULSE THEREBY UNTIL THE PREVIOUS PULSE PROPAGATES TO THE END OF SAID DELAY LINE, A RANDOMLY ACCESSIBLE MEMORY CAPABLE OF BEING SELECTIVELY CHOSEN FOR ACCESS BY SAID PROCESSOR IN ANY ONE OR MORE OF SAID OPERATING CYCLES, MEANS INCLUDING PROCESSOR ADDRESS MEANS AND PROCESSOR INPUT-OUTPUT MEANS FOR COOPERATING WITH SAID MEMORY TO PERMIT PERFORMANCE OF A MEMORY CYCLE DURING WHICH A SELECTED ADDRESS IN MEMORY IS ACCESSED IN ACCORDANCE WITH SAID PROCESSOR ADDRESS MEANS, PROCESSOR MEMORY ACCESS INDICATING MEANS FOR INDICATING WHEN THE PROCESSOR IS USING THE MEMORY, PROCESSOR MEMORY REQUEST INDICATING MEANS FOR INDICATING WHETHER THE PROCESSOR REQUESTS ACCESS TO THE MEMORY DURING THE NEXT PROCESSOR CYCLE, AT LEAST ONE PERIPHERAL UNIT INCLUDING PERIPHERAL ADDRESS MEANS AND PERIPHERAL INPUT-OUTPUT MEANS CAPABLE OF COOPERATING WITH SAID MEMORY IN THE SAME MANNER AS SAID PROCESSOR ADDRESS MEANS AND SAID PROCESSOR INPUT-OUTPUT MEANS, GATING MEANS FOR GATING SAID ADDRESS MEANS AND SAID INPUT-OUTPUT MEANS SO AS TO PERMIT EITHER THE PROCESSOR ADDRESS AND INPUT-OUTPUT MEANS OR THE PERIPHERAL ADDRESS AND INPUTOUTPUT MEANS TO ACCESS SAID MEMORY INDEPENDENTLY OF ONE ANOTHER, SAID PERIPHERAL UNIT ALSO INCLUDING PERIPHERAL REQUEST INDICATING MEANS FOR INDICATING WHEN SAID PERIPHERAL UNIT REQUESTS ACCESS TO SAID MEMORY, MEANS COUPLED TO SAID PROCESSOR MEMORY REQUEST INDICATING MEANS AND SAID PERIPHERAL REQUEST INDICATING MEANS FOR INHIBITING GENERATING OF A NEW PROCESSOR CYCLE WHEN BOTH SAID PROCESSOR AND SAID PERIPHERAL UNIT REQUEST ACCESS TO THE MEMORY FOR THE SAME PERIOD, AND MEANS COUPLED TO SAID PERIPHERAL REQUEST INDICATING MEANS AND SAID PROCESSOR MEMORY ACCESS INDICATING MEANS FOR PERMITTING SAID PERIPHERAL UNIT ACCESS SAID MEMORY VIA SAID GATING MEANS WHEN SAID PROCESSOR IS NOT ACCESSING THE MEMORY. 